1. Field of the Invention
This invention relates generally to mapping techniques for semiconductor substrates. More specifically, the present invention relates to methods and apparatus for identifying defective die sites and good die sites on semiconductor mounting substrates of any type and, if necessary, attaching defective dice to the defective die sites and, if necessary, attaching good dice to the good die sites.
2. State of the Art
In the fabrication of semiconductor die packages, semiconductor dice (also known as “semiconductor devices” or “semiconductor chips”) are typically mounted and electrically connected to carrier substrates appropriate for the chip type and the subsequent use of the package. For example, chip-on-board (COB), board-on-chip (BOC), ball grid array (BGA), chip-scale, or leads-over-chip (LOC) mounting arrangements may be made on printed circuit board strips, tape frames and other carrier substrates known in the art. After die attach (the mounting of the semiconductor die to the carrier substrate), the hybrid combination of components is electrically connected, generally through wire bonding, conductive adhesives or solder reflow and encapsulated for protection. The finished package is then made available for use in a wide variety of applications.
Semiconductor dice and carrier substrates are distinct components which are manufactured by separate processes. Individual integrated circuit dice are usually formed from a larger structure known as a semiconductor wafer, which is typically comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide are also sometimes used. Each semiconductor wafer has a plurality of integrated circuit semiconductor dice and/or circuitry, arranged in rows and columns with the periphery of each integrated circuit being substantially rectangular in shape, the integrated circuits of the semiconductor dice being formed through a combination of deposition, etching, and photolithographic techniques. The inactive silicon back sides of the wafers are typically thinned (i.e., have their cross-sections reduced) by a mechanical and/or chemical grinding process, and the wafers sawed or “diced” into substantially rectangularly shaped discrete integrated circuit semiconductor dice. The nature and complexity of the process for fabricating integrated circuits make the manufacturing cost of an individual semiconductor die relatively high.
With respect to the various carrier substrates for COB, BOC, BGA, LOC, chip-scale, and other types of packages, each of the carrier substrates is generally manufactured with several common features: an attachment site for at least one semiconductor die, a plurality of bond pads and conductive traces for interconnecting conductors on one or more semiconductor dice, a resist or insulating layer for electrically isolating the conductive traces and interconnections, tooling holes on the substrate edges for automated machine handling, and alignment marks for semiconductor die placement, wire bonding, and substrate orientation. The electronic properties and performance of the carrier substrate are determined by precise characteristics of the conductive layers and insulation layers which form it, including the composition, thickness, and surface quality of the various types of layers.
Currently, many carrier substrates (also referred to as “mounting substrates”) have multiple die attach sites per carrier substrate, which may further be formed in an array arrangement of several across or a matrix of columns and rows. Such high-density arrays or matrices are suitable for increased throughput in automated processing, such as die attach processing, as well as desirable for use in various electronics applications. The array or matrix of die attach sites of any given substrate may range, for example, from a 2×3 matrix (2 columns×3 rows) to a 20×20 matrix. Typically, a 2×3 matrix for a BGA-type carrier substrate 10 is depicted in drawing FIG. 1. Semiconductor die sites 20, for mounting and electrical attachment of a semiconductor die to each site 20, are configured in an arrangement of two columns and three rows. Pin one indicators 22 and fiducial marks 24, which provide orientation for vision systems associated with automated machine handling and semiconductor die placement apparatus (not shown), are formed as openings in a layer of solder resist 26 on carrier substrate 10. Semiconductor die sites 20 are shown with solder balls 32 of the BGA surrounding each semiconductor die receiving area 50 and configured in a ball grid array arrangement 54. The solder balls 32 are typically placed on contact pads (not shown), which are further electrically interconnected to circuit traces (not shown) underlying a passivation layer of solder resist 26 on the surface of the carrier substrate 10. The circuit traces are, in turn, electrically connected to other contact pads within or immediately proximate to semiconductor die sites 20.
After die attach, conductive wires extending from the active surface of the mounted semiconductor die are typically wire bonded onto the contact pads in the semiconductor die site 20 of the carrier substrate 10. The conductive traces, contact pads, and other contact pads are typically formed by laminating or depositing a metal material (e.g., copper) onto a base insulating substrate material. Subsequent photolithographic and etching techniques are then used to define the actual conductive patterns.
Referring again to drawing FIG. 1, carrier substrate 10 also includes a layer of solder resist 26. The layer of solder resist 26 is applied using photolithographic processes onto carrier substrate 10 and serves to mask or shield conductive members on the top and bottom carrier substrate surfaces during subsequent soldering and/or plating processes and/or various other processes. Various solder resist materials are well known and commercially available for such processes. With respect to the surface of carrier substrate 10, layer of solder resist 26 may mask all portions of the surface except the semiconductor die sites 20 and the contact pads for placement of solder balls 32. As previously described, pin one indicator 22 and fiducial marks 24 are typically formed as openings in the layer of solder resist 26 subsequent to the deposition thereof. Any conductive elements within semiconductor die site 20 thus remain exposed, as does at least a portion of the contact pads, after application of the layer of solder resist 26 to the top surface of the carrier substrate 10.
In the process of die attach, a die attach apparatus typically uses a vision system to locate a fiducial mark 24, pin one indicator 22, and/or any other alignment feature on the lead frame or other mounting substrate. Using an X-Y table for proper alignment, the vision system checks the semiconductor die position on the die pickup tool and directs the apparatus to adjust the substrate and die pickup tool into the correct positions for precise semiconductor die placement. Typically, semiconductor dice are presented to a die attach apparatus in sawed wafer form and are mounted on wafer tape for attachment on metal lead frames or any suitable substrate. For some die attach apparatus, semiconductor dice may also be presented in gel or waffle pack form for attachment to the desired substrate. In the die bonding process, semiconductor dice are selectively picked from those of wafers respectively probe-tested in their manufacturing factories using various testing equipment. To orient the semiconductor dice, the die bonder's vision system identifies a feature on a die and directs the X-Y table to pick up and align the die in the X, Y, and theta directions. Meanwhile, a mounting substrate has been indexed to the die attach site and properly oriented. At the die attach site, a precise amount of adhesive, such as epoxy resin, is applied. The picked-up die is then bonded to the die attach site of the mounting substrate via the adhesive.
Since semiconductor dice are high-grade products with highly integrated structures, the cost per semiconductor die is relatively high. As such, prior art die attach processes tend to focus on methods of dealing with defective semiconductor dice and not defective die sites on a mounting substrate.
In each batch of manufactured semiconductor dice and substrate components, a small percentage of the substrate components will be defective. In an effort to minimize the costs and maximize the quality of assembled packages, steps are typically taken to ensure that only semiconductor dice and substrate components which are found to be functional are assembled with one another. Therefore, prior to the die attachment process, wafers, semiconductor dice and carrier substrates are typically tested for electrical defects, contamination, and other irregularities. Semiconductor dice and substrates that are found to be defective are typically marked in a manner so as to distinguish them from known good components.
There are numerous teachings relating to the marking and/or mapping of defects in semiconductor wafers and semiconductor dice. One method for marking used extensively in the semiconductor industry is to use colored ink dots to label semiconductor dice which have failed testing procedures. These ink dots can be read by a vision system for automated pick-and-place processing. For example, U.S. Pat. No. 5,654,204 to Anderson discloses a process in which a wafer is electronically mapped, individual semiconductor dice are tested, and a wafer map identifying the defective semiconductor dice is produced and provided to an automated inking apparatus.
In U.S. Pat. No. 5,256,578 to Corley et al., a method for wafer map recording is disclosed wherein individual active dice are tested for functionality while in wafer form. The active dice are then categorized based on functional results, and the testing results are summarized on a wafer map. A binary code is then generated which contains the entire wafer map information. This information is recorded on the semiconductor wafer by laser scribing, and the results used for either manual or automated die selection.
In U.S. Pat. No. 6,021,380 to Fredriksen et al., a scanner is employed to produce a virtual image of the wafer, identifying all chips even when diced apart. A vision system uses the virtual wafer image to sort out defective chips, and gross defects identified by the vision system process are classified and marked in a computer-stored wafer map.
Various patents, such as U.S. Pat. No. 5,175,425 to Spratte et al., U.S. Pat. No. 4,585,931 to Duncan et al., and U.S. Pat. No. 4,510,673 to Shils et al., are directed to assorted other semiconductor marking techniques. The patents to Spratte et al. and Duncan et al. disclose processes for laser marking and identifying semiconductor wafers with a machine readable bar code, while the patent to Shils et al. discloses a method of laser marking the back side of individual dice with a unique identifying code.
The prior art of identifying and marking defective carrier substrates is less expansive than the art dealing with defective semiconductor wafers or dice. When irregularities are found on individual die sites of a carrier substrate strip, the entire strip is ordinarily not rendered unusable unless a substantial number of the die sites are found to be defective. For some strips, defective sites constituting 10% or greater of the total number of die sites will justify discarding the entire strip. In other strip arrays, higher numbers of defective die sites are tolerated. When a defective die site is identified on a substrate, typically by automated testing apparatus or a vision system, conventional practice is for an operator to manually “x-out” or “ink-out” a feature of the defective die site, rendering the feature “unreadable” by the vision recognition system of an automatic die bonding apparatus. A relatively simple system of vision recognition is a black and white digital recognition system (DRS), which can recognize inked-out features and streets between die attach sites. In more sophisticated operations, a pattern recognition system (PRS) is used as a vision system to identify defects and to recognize inked-out features. The PRS can also be used to align a bond pad with a die.
The“inking out” is usually accomplished by marking over an exposed feature in the solder resist which is a component of the defective die site, completing the mark with an ink pen, for example. As used herein, the term“exposed feature” denotes an opening in the solder resist which typically exposes a visibly discernible Au/Ni/Cu surface. Features which are commonly“inked out” include pin one indicators, bond pads, and/or fiduciary marks, as shown, for example, in drawing FIG. 1, illustrating inked-out marks 34 over pin one indicators 22, where the semiconductor die sites 20 have been found defective. Accordingly, during the die attach process, defective semiconductor die sites 20 do not receive dice attached thereto and the good semiconductor die sites 20 do receive dice 52 attached thereto.
It is also the case, however, that automated processes for the marking of defective substrates have been known in the art. U.S. Pat. No. 4,437,229 to Bitler et al. discloses a method of marking defective electronic articles in an array arrangement. The method entails forming film circuit articles in the array with added test pads and resistive elements and electrically altering a resistive element to a relatively high resistive value when a defective circuit is found. The article substrate (an array of film circuits) is subsequently fed into a holding apparatus which measures the resistive value of the resistive element, thereby labeling the substrate as acceptable or defective. The holder then transfers this data to a microprocessor within a die bonding apparatus. The die bonder then directs chips to be bonded only to those array circuits which have been labeled as functional by virtue of their low resistive values. As such, array circuits with any defective elements therein are discarded, even though many of the circuits in the array may be acceptable.
U.S. Pat. No. 4,787,143 to Yagi et al. discloses a method for applying a code mark to a substrate to which electronic parts are to be mounted. The code mark, which may be a bar code, is formed on the substrate prior to the mounting of a semiconductor die. Once the semiconductor die is mounted on the substrate, a mounting failure detection mechanism on a die mounting apparatus serves to automatically detect an incorrect or defective mounting of the die. The mounting failure detection system is further configured with a code reader for reading the code mark of each substrate and a control box for generating mounting failure data. Yagi et al. teaches that when a mounting failure has been detected, a mounting failure data edit controller collates mounting failure data supplied from the control box with the code signals from the code reader, then uses the data to classify and automatically separate defective substrates from good ones. Although Yagi et al. eliminates defective substrates, Yagi et al. only determines such defects after the dice are mounted on the substrate; thus, such defects are discovered irrespective of the dice or the substrate alone, potentially resulting in the loss of good dice mounted to already defective die attach sites.
U.S. Pat. No. 5,197,650 to Monzen et al. teaches placing an identifier, preferably a bar code, on a lead frame prior to the mounting of semiconductor dice thereon. Semiconductor dice are first tested, then mounted to the lead frame. As the dice are mounted, an information processing unit adds information about the lead frame to the semiconductor die test results. The accumulated data is then forwarded to the next phase of the packaging process, which may be wire bonding, for example. The wire bonding apparatus receives the combined data and uses it accordingly to perform wire bonding operations. Monzen et al., however, does not teach that the bar code contains information about defective semiconductor die sites. Instead, Monzen et al. teaches that as the dice are mounted to the lead frame, the identifying information on the bar-coded lead frame is combined with the semiconductor die test results to be employed at later stages after semiconductor die bonding.
As can be seen from the foregoing, the prior art automated processes dealing with defective carrier substrates sacrifice good semiconductor dice to be attached to defective die sites, in which such good dice are discarded. With respect to the method of manually inking-out a defective semiconductor die site, it is troublesome and inefficient. Furthermore, when a carrier substrate with one or more inked-out die sites is placed in an automated die attach apparatus, data from the digital or pattern recognition system and/or testing systems is fed into a processor. The processor interpreting the data instructs the die attach apparatus to skip over the defective die sites. As a result, the carrier substrate may include several unoccupied die attach sites (die attach sites without semiconductor dice attached thereto), as shown in drawing FIG. 1.
However, unoccupied die attach sites present several problems, namely problems relating to the structural integrity of the carrier substrate and the finished semiconductor die package. With respect to structural integrity, the carrier substrates are designed and formed with the intention of carrying a semiconductor die attached to each of the multiple die attach sites on the carrier substrate. Such attachment of the semiconductor dice provides strength to the carrier substrate in order to handle the processes associated with fabricating the semiconductor die package. Without each of the die attach sites having a die attached thereto, the structural integrity and mechanical reliability of the carrier substrate is compromised. This problem is only exacerbated with the ongoing advances of semiconductor technology, resulting in the miniaturization of semiconductor components, which includes carrier substrates having thinner size specifications.
Furthermore, another problem associated with carrier substrates not having a die attached to each of the die attach sites involves encapsulating the carrier substrates via a transfer molding operation. In particular, encapsulant volume requirements for filling mold cavities is varied due to unoccupied die attach sites on the carrier substrate. Such variable volume requirements either result in waste which is costly and inefficient use of the encapsulation material or result in a shortage of encapsulation material which produces defective packages.
To illustrate a transfer molding operation, drawing FIGS. 2A and 2B show premolding and postmolding positions using a typical mold apparatus comprising upper and lower mold halves 110 and 112, each mold half including a platen 114 or 116 with its associated chase 118 or 120. Heating elements 122 are employed in the platens to maintain an elevated and relatively uniform temperature in the runners and mold cavities during the molding operation. FIG. 3 shows a top view of one side of the transfer mold apparatus of drawing FIGS. 2A and 2B illustrating the above-noted problem of having a shortage of encapsulation material. In the transfer mold apparatus shown, the encapsulant flows into each mold cavity 144 through the short end thereof.
In operation, a heated pellet of resin mold compound 130 is disposed beneath ram or plunger 132 in pot 134. The plunger descends, melting the pellet and forcing the melted encapsulant down through sprue 136 and into primary runner 138, from which it travels to transversely oriented secondary runners 140 and across gates 142 into and through the mold cavities 144 through the short side thereof flowing across the carrier substrate 10, wherein carrier substrate 10 comprises dice 52 attached thereto, such as an array of six dice attached to a carrier substrate for positioning in and across six mold cavities 144 shown in drawing FIG. 3. Air in the runners 138 and 140 and mold cavities 144 is vented to the atmosphere through vents 146 and 148. With this arrangement, since the pellets of resin are substantially consistent in size, the melted pellets or encapsulation material thereby includes a substantially consistent volume, resulting in the shortage of encapsulation material for the transfer molding operation when having unoccupied die attach sites. Such encapsulation shortage as illustrated in drawing FIG. 3 results in defective packaging of dice.
Accordingly, what is needed in the art is a method and apparatus for maintaining the structural integrity of the carrier substrate and preventing defects in the encapsulant mold and the waste thereof that are automated, accurate, low cost, relatively simple, and include high throughput.